HDL Express

Welcome to HDL Express, the personal webpages of Kirk Weedman

HDL stands for Hardware Description Language.

This website also contains information on various Verilog/FPGA tutorials, Alternative Energy projects, and the progress of a new CPU architecture that I'm designing.

I'm an electronic design engineer specializing in contract Verilog RTL FPGA design, functional verification, testbench creation, simulation and debug. I have a varied background in other disciplines too.

My resume: Download the PDF version here. Download Word format here

Availability for new FPGA design/debugging contract work - October 2018

TIP Algorithm - a new dynamic instruction scheduling algorithm

Oct, 2017: Current Status of the new Out of Order CPU Architecture based on the TIP algorithm

This new dynamic instruction scheduling algorithm is not like the typical OoO methods being used today and the goal is to improve OoO IPC. Most Modern Out of Order CPU's, either use the Tomasulo or Scoreboarding algorithm (or some variant) for dynamic instruction scheduling. The method used in this CPU is completely different and simpler although there are several specific rules it follows. There is no register renaming, as the method effectively has infinite renaming, and thus no physical register set, just the architectural registers. It appears the logic for the this new algorithm grows fairly linear as IPC increases linearly instead of exponentially like the Tomasulo algorithm. The goal of building a working CPU is to prove the method works and to vary design parameters to get maximum performance (IPC throughput) for a given microarchitecture.

4/27/2017 - Since this algorithm can be applied to most any ISA, I am switching from the ARMv7 ISA to the RISC-V (RV32IM). RISC-V will be simpler to implement and there is software tool support for it.

See CPU History for more information about the progress on this architecture

See Branch Prediction Elimination for more info about the progress on this method.

1. 7/13/2018 - New s block diagram of new Out of Order Microarchitecture

2. Debugging RV32IM instructions & flow through front end stages.

3. Adding RISC-V CSR instructions to the decode, addding integer multiply and divide, etc..modules

4. Creating RTL for an L1_ICache and a 32KB 8-way Set Associative L1_DCache.

5. Creating a new RTL version of Fetch.

6. Defining a new/improved Reservation Station that will work with instruction branching. This will replace LLRS.

7. Various functional simulations going on.



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