RisKy1 Project

Welcome to the RisKy1 CPU Project web pages

This website contains information for the RisKy1 CPU. It will be a 5 stage pipelined RISC-V pipelined CPU with documentation and presentations describing the design.

Initial CPU will be based on the RV32I instruction set, but will eventually support options for other CPU versions.




RisKy1 website created 9/29/2019 - Under Construction!

Goals include:

1. A documented System Verilog design

2. Open Source code that is highly parameterized to create different versions of RISC-V CPUs

3. Tutorials for others to learn the how to install FPGA tools, create projects, compiling & simulating code on tthe RisKy1. Implementing it an FPGA, program an FPGA, creating C and assembly code using the free RISC-V compiler, tutorials, etc..

4. Use free tools as much as possible - at least for a smaller FPGA design.

This website will explain how to setup this project on a Windows 7 or 10 machine in the "How to..." section.

For questions, comments, improvement suggestions about this project, please contact Kirk Weedman - get my contact info from my resume on my main website webpage www.hdlexpress.com