If you interested in working on this project, I have a unique offer. I am just an individual Engineer working on this and currently not employed. I'm taking time off to create this new CPU architecture. Thus I can't offer monetary compensation. However I can offer you help in learning various engineering design techniques and experience. You will work remotely. You can work as little or as much as you like on this. I have been an engineer for over 30+ years, of which the last 15+ have been in Verilog RTL & Behavioural coding, design, simulation, debug, etc.. Listed below is what I'm looking for and what you will be doing.

Mandatory skills:

1. Someone with basic knowledge and experience in Verilog RTL and Behavioural coding. You do not have to have years of experience.

What I expect:

No sharing with anyone of Verilog code or ideas related to this project. Willing to sign an NDA if/when requested. Initial work does not reveal the patent method but no related info or techniques should be be shared. You must have a willingness to document and code in the style I am using. You should be willing to ask me questions about why things are done a certain way and offering improvement suggestions in coding, organization, documentation, simulation, test benches, test methods/procedures, etc.. if you think something can be done better.

Skills that would be good to have:

1. Knowing how to create Verilog test benches.

2. ModelSim Experience

3. Debugging experience

4. Familiar with the ARMv7 ISA

5. Xilinx ISE experience

6. IAR Workbench experience related to ARM

7. Tortoise SVN experience


What you will be doing:

1. Setting up the necesary tools to work: ModelSim, Xilinx ISE, IAR Workbench, NotePad++, Tortoise SVN - on Windows 7.

I will show you how to setup the tools and projects.

2. The immediate need is to create test benches for simulation of the front end portion of the CPU. This will include the Fetch, Decode/Tag, and Microcode modules which are related to the ARM ISA I'm currently using. You will learn how to debug these portions of the code as well as debugging the debug_asm.v module during simulation. I will help you get started in all of this. Xilinx ISE will not be used initially. It will get used later in the project once modules are debugged so I can be sure the RTL is synthesizable for FPGA or ASIC use.

3. We will need to do some remote screen sharing from time to time to explain things. For example, I may want to walk you through some code, or show you something that's simulating on my computer, or help you debug something you are simulating. We can determine the best method together.

If interested contact me. kirk@hdlexpress.com

Send me a resume or just tell me what skills you have related to the above. Also tell me why you are interested in helping and how much or how little you might be able to help. Also tell me what you expect to learn - i.e. what areas of help you might need. I want this to be mutually beneficial. I'm not expecting someone with a lot of experience. I will post credit on my website for those that make contributions to the work.