Verilog Tutorials
Various tutorials as I have time to make them.
Dec 25, 2019: Integer Division.
This is a new method I created for doing integer division for a RISC-V CPU.
Jan. 2015: The UART Project.
This project does use a simple UART that interfaces to a terminal/console window on a PC, but it's to show how to create a project from scratch using the Xilinx ISE tools as well as a briefly showing how to create IP with COREGEN for this project. Anyway, hope you enjoy it.
Download project files here and the hi res video tutorial MPEG here.
Mar. 31, 2013: CORDIC Design and Simulation using Verilog
This is a newer updated version of the one shown further below. This is a generic CORDIC to produce sine and cosine type outputs and does not have some extra baggage as the older version did, due to its use in a Software Defined Radio.
The design and simulation files can be downloaded from here and a good resolution MP4 here.
The following tutorials were created while I was doing some Software Defined Radio (SDR) work on the openhpsdr.org website in 2009.
These tutorials will teach you the basics of Verilog. These are from a live webinar I did which had an audience of people from all around the world. The audio quality is not the greatest, especially in the first lecture. Maybe in the future I'll redo them. The lectures also show use the use of ModelSim during certain portions of the lectures. There may be a few mistakes in these lectures so be nice :) and feel free to email me and ask questions. If I'm not too busy, I'll try to answer. You can find my contact info in my resume on the main home page.
Verilog Basics Tutorial 1 of 10 - Click here to see the full resolution version on YouTube.
Click here to download the labs associated with this lecture.
Verilog Basics Tutorial 2 of 10 - Click here to see the full resolution version on YouTube.
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Verilog Basics Tutorial 3 of 10 - Click here to see the full resolution version on YouTube.
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Verilog Basics Tutorial 4 of 10 - Click here to see the full resolution version on YouTube.
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Verilog Basics Tutorial 5 of 10 - Click here to see the full resolution version on YouTube.
Click here to download the labs associated with this lecture.
Verilog Basics Tutorial 6 of 10 - Click here to see the full resolution version on YouTube.
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Verilog Basics Tutorial 7 of 10 - Click here to see the full resolution version on YouTube.
Click here to download the labs associated with this lecture. This video may require the GoToMeeting codec to play.
Verilog Basics Tutorial 8 of 10 - Click here to see the full resolution version on YouTube.
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Verilog Basics Tutorial 9 of 10 - Click here to see the full resolution version on YouTube.
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Verilog Basics Tutorial 10 of 10 - Click here to see the full resolution version on YouTube.
Click here to download the labs associated with this lecture.
CORDIC - as used in a Software Defined Radio Implementation.
This tutorial was created to show how to design a CORDIC that can produce both sine and cosine functions in Verilog. Simulation in ModelSim is also shown as well as a few other things. This is from a live online presentation given to a group of individuals involved in Software Defined Radio. Click here to see the full resolution version on YouTube. Click here to download and save the Verilog code and ModelSim setup mentioned in this lecture.
CORDIC webinar: I did not explain something in the kordic.v code that I should have. There are several equations in Stage 0 that are of the following format:
X[0] <= {Xin[WI-1], Xin} << (EXTRA_BITS-1); // since An = 1.647, divide input by 2 and then multiply by 2^EXTRA_BITS
Y[0] <= {Yin[WI-1], Yin} << (EXTRA_BITS-1);
I told you that we divide by 2 then multiply by 2^EXTRA_BITS but I didnt tell you WHY we divide by 2. Notice that the overal gain due to the CORIDC iterative process where the Ki's are removed from each iteration gives us an overall gain of 1.647. Therefore to get the gain back to unity we should multiply by 1/1.647 = .6073. This implementation in kordic.v as well as that of cordic.v takes a simplistic approach and multiples by 1/2 = .5. Not the ideal .6073, but OK. We could get closer to unity by doing something like 1/2+1/16+1/32 = .59375 or maybe something even better.
Keep in mind this was for a Software Defined Radio project and the CORDIC code has a couple extra things in it that are not necessary such as a angle_accumulator and EXTRA_BITS. I am currently working on creating a better presentation about CORDIC that doesn't have any SDR related stuff in it and will be a general purpose sin/cos CORDIC. I may work on presentations using CORIDC for other functions in the future.
Using GTKWave
This brief tutorial is about getting GTKWave up and running on Windows. Click here to download GTKWave3.1.6
Click here to see the full resolution video on YouTube