RisKy1 Project

Downloads - Videos, Source Code, SW, etc..

 

Here you will find videos discussing the Verilog design, the open source code of the design, free software dowhloads, etc..

 

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Note: 2/24/2020 - To download the RisKy1 CPU related files and videos, you need to be an active and registered participant. Please contact kirk at hdlexpress dot com.

CPU Design Sessions (videos and related source code)

This is the current series of video sessions telling about the CPU code design and also actual design (Verilog code) files related to the video. These videos are being created as the design is being created, so the Verilog code will be changing from one session to another until the design is completed. To save these mp4 and zip files, right click on the link and select "Save Link As" to a location on your PC. Videos can also be viewed on this website by just clicking on them.

Session 1

Video

7/29/2019 - Video of the first session on designing the RisKy1 CPU

Code

7/29/2019 - Zip file of the System Verilog files used in the Session 1 video

Session1 covered the following:

1. Project Overview
2. Free Tools that we'll use. Where to get and how to install and setup to use them
3. Coding: We'll dive right in to the Decode Stage design using Verilog/System Verilog. Several "include" files for this decode design will be discussed because they will be used in future design sessions.
4. Coding: GPR registers

Session 2

Video

8/22/2019 - Video of the second session on designing the RisKy1 CPU

Code

8/22/2019 - Zip file of the System Verilog files used in the Session 2 video

Session 2 covered the following:

Review/questions about Session 1
1. Design of RisKy1_core top level module that will instantiate the Fetch, Decode, Execute, Memory, Write Back, GPR, etc. modules and their interconnecting signals.
2. Design of Execute Stage with connections to various Functional Units
3. Design of ALU, Branch, Integer Multiply Functional units.
4. Forwarding logic

Session 3

Video

9/5/2019 - Video of the third session on designing the RisKy1 CPU

Code

9/5/2019 - Zip file of the System Verilog files used in the Session 3 video

Session 3 covered the following:

1. Design of Load/Store Functional Unit.
2. Design of CSR Functional Unit (this will not include the actual CSR registers as defined in Privileges spec)
3. Design of Write Back Stage

Session 4

Video

10/15/2019 - Video of the fourth session on designing the RisKy1 CPU

Code

9/20/2019 - Zip file of the System Verilog files used in the Session 4 video

Session 4 will cover the following:

1. Updates made to decode.sv, decode_core.sv, execute.sv, gpr.sv, ls_fu.sv and RisKy1_core.sv
2. New modules csr.sv (not csr_fu.sv), and fetch.sv. Most of the video is about fetch.sv

Session 5 Video 11/7/2019 - Video of the fifth session on designing the RisKy1 CPU
Code 11/6/2019 - Zip file of the System Verilog files used in the Session 5 video

Session 5 covers the following:

1. Addition of mem_io.sv, irq.sv
2. Fixes to fetch.sv, exe.sv, RisKy1.sv...
3. csr.sv is now combined with the older csr_fu.sv and the result is a new csr_fu.sv (inside execute.sv)
4. Addition of a lot of logic to csr_fu.sv is in the form of new include files csr_rd_mach.svh, csr_rd_super.svh, csr_rd_user.svh, csr_wr_mach.svh, csr_wr_super.svh, csr_wr_user.svh...

Session 6 Video 11/30/2019 - Video of the sixth session on designing the RisKy1 CPU
Code

11/28/2019 - Zip file of the System Verilog files used in the Session 6 video

Session 6 covers the following:

1. Logic for WFI and ECALL instructions
2. modifications due to #1 and a few fixes to various modules.
3. Addition of Immediate Assertions to various modules.
4. Simulation discussion about the Decode stage, how decode works and how to observe the signals in the simulation

Session 7 Video 12/23/2019 - Video of the 7th session on designing the RisKy1 CPU
Code 12/23/2019 - Zip file of the System Verilog files used in the Session 7 video.

Session 7 will contain the following

1. All assertions will now be placed in their own files and be bound to a specific module. All assertions are usable in questasim, but not all in Modelsim. Placing them in separate binding files will help prevent code clutter in the main modules. For example, wb_asserts.sv is bound to wb.sv in the top level simulation module top_tb1.sv using the following which could easily be commented out for debugging purposes.

bind wb wb_asserts b3 (.*);

2. New assertion files gpr_asserts.sv, mem_asserts.sv, RisKy1_asserts.sv, wb_asserts.sv
3. Updates to L1_icache.sv and fetch.sv
4. L1_dcache.sv - added logic to handle Load/Stores that cross a cache line boundary - untested.
5. Fixes to CSR logic
6. EBREAK logic added
7. Exception causes updated
8. Integer Unsigned Divide(with Remainder) logic added

Youtube

Video about my new unsigned integer divide algorithm. Posted 12/25/2019 - my gift to the public :)

Code for integer divider with testbench (no username/password needed to download)

Session 8 Video 1/15/2020 - Video of the 8th session on designing the RisKy1 CPU
Code

1/15/2020 - Zip file of the System Verilog files used in the Session 8 video.

WARNING: 1/16/2020: you will need to edit idr_fu.sv and change div_N_by_N to sdiv_N_by_N.

Session 8 will contain the following:
1. Speed improvement and logic reduction for signed division and a separate testbench for testing it.
2. sdiv_N_by_N.sv supports both signed and unsigned integer division -> completion of M extension.
3. Additions to decode_core.sv for 16 bit Compressed Instructions
4. Fixes to csr_rd_user.svh (counter reading logic - 0xC00-0xC1F, 0xC80-0xC9F)
5. Addition of cpu_params.svh parameter checks at compile time to check for "parameters" out of range
6. Addition of RISCV_FORMAL information (not completed yet) to hopefully test RisKy1 in the future using formal verification - see https://github.com/SymbioticEDA/riscv-formal

7. Cleanup of all CSR logic. Using csr_<name> now instead of csr[addr]. Code should be easier to read.

Session 9 Video Jan. 27, 2020 - Video of the 9th session on designing the RisKy1 CPU
Code Jan 23, 2020 - Zip file of the System Verilog files used in the Session 8 video.

Session 9 will cover the following
1. New gen_rand_instr.sv module to generate 21 different types of constrained random instructions and places them in a file for simulation. They can be be automatically checked for correct operation in simulation by "binding" RisKy1_asserts.sv to the simulation. Load, Store and Branch instructions are not generated in gen_rand_instr.sv.
2. Fixes/updates to RisKy1_asserts.sv
3. mis-spoke in last video about S & U modes. Changing add_S and add_U to ext_S and ext_U
4. fixes to interrupt logic & CSR mtval
5. fixes to mem_io.sv
6. fixes to Return Address Stack prediction logic in fetch.sv

Session 10 Video March 4, 2020 - update to video posted 3/3/2020 at time 14:56.
Code Mar 2, 2020 - Code cleanup, decode_core.sv & disasm.sv rewrite, I/O changes/additions

Note: I used the tool Synplify Pro (targeting an FPGA to see if code is synthesizable) to make sure the code was RTL compatible. You can download a free version of Synplify Pro from Microsemi.. Even though you can only target Microsemi FPGAs with this tool, you can use the tool to check your RTL code. Get the free yearly Silver license. I believe Quartus FPGA tools also include Synplify Pro.

Session 10 will cover the following:
1. Addition of external I/O bus & control signals to RisKy1_core.sv and mem_io.sv - can be used for connecting peripherals to CPU
2. Redesign of decode_core.sv and disasm_RV.sv

Release 11 Code April 4, 2020 - Code fixes due to debugging and a Formal test I'm developing

1. disasm_RV.sv updated to match decode_core.sv with HINTS added
2. decode_core.sv - fixes
3. L1_dcache.sv & L1_icache.sv fixes
4. mem_arb_mode.sv fixes
5. cpu_structs.svh changes
6. Various files fixes - top_tb1.sv, top_tb1.do, RisKy1_core.sv, mem.sv

Overall structure still basically the same. Just making bug fixes.

Release 12 Code May 4, 2020 - Some code fixes due to using Formal verification

1. GPIO removed as it really shouldn't be in the core.

2. Fixes due to finding design issues using Formal Verification type tools

Release 13 Code May 12, 2020 - ADDI logic and CSR updates
Release 14 Code May 19, 2020 - CSR related logic updates, disasm.sv updates
Release 15 Code June 3, 2020 - bug fixes and new support logic for branch prediction
Release 16 Code July 8, 2020 - Some subtle bugs have been found due to property firings using a Formal Property Verification tool. Currently for RV32i there are over 330 property checks being used, including a few for exceptions and CSRs
Release 17 Code July 20, 2020 - Fixes due to Formal Property Verification work, updates to Compressed instruction logic names, addition of more Single Precision Floating Point logic and some code cleanup.
Release 18 Code August 27, 2020 - Fixes (fetch, decode, execute, ext_S, CSRs, interrupt). Continuing Formal Property Verification - currently 305 out of 319 properties are passing. Also started working on debugging ext_C (Compressed instructions) with Formal Property Verification
Release 19 Code Sept 7, 2020 - MRET, SRET, URET logic updates. execute.sv, br_fu.sv,cpu_struct.sv, decode_core.sv fixes. Fetch.sv was heavily modified due to debugging of Compressed instructions.

This is a new RISC-V CPU design in progress.

Current Status: Formal Property/Equivalency Verification techniques are being used (using SVA - Assertion Based Verification) for debuging the design

This design is very versatile. An RV32, 5 stage pipeline CPU can be built in many different configurations by changing user definable parameters.

Help is currently needed in checking CSR code, instruction verification/debug, creating and checking assertions, and just general testing by creating and running simulations of SW. If you would like to help, please contact me.

 

Free Software

RISC-V Software Ecosystem See https://riscv.org/software-status/
Microsemi Downloads Download the free Libero SoC Design Software which includes Synplify ProME. You can also get a 1 year free Silver license. Although you can only target Microsemi devices, you can use Synplify to check that you are creating synthesizable RTL code.

 

RISC-V Specifications

See https://riscv.org/specifications to see if there are more recent versions

The RISC-V Instruction Set Manual Volume I: Unprivileged ISA
The RISC-V Instruction Set Manual Volume II: Privileged Architecture
RISC-V External Debug Support specification