RisKy1 Project

Downloads - Videos, Source Code, SW, etc..

 

Here you will find videos discussing the Verilog design, the open source code of the design, free software dowhloads, etc..

 

 

 

 

CPU Design Sessions (videos and related source code)

This is the current series of video sessions telling about the CPU code design and also actual design (Verilog code) files related to the video. These videos are being created as the design is being created, so the Verilog code will be changing from one session to another until the design is completed. To save these mp4 and zip files, right click on the link and select "Save Link As" to a location on your PC. Videos can also be viewed on this website by just clicking on them.

Session 1

Video

7/29/2019 - Video of the first session on designing the RisKy1 CPU

Code

7/29/2019 - Zip file of the System Verilog files used in the Session 1 video

Session1 covered the following:

1. Project Overview
2. Free Tools that we'll use. Where to get and how to install and setup to use them
3. Coding: We'll dive right in to the Decode Stage design using Verilog/System Verilog. Several "include" files for this decode design will be discussed because they will be used in future design sessions.
4. Coding: GPR registers

Session 2

Video

8/22/2019 - Video of the second session on designing the RisKy1 CPU

Code

8/22/2019 - Zip file of the System Verilog files used in the Session 2 video

Session 2 covered the following:

Review/questions about Session 1
1. Design of RisKy1_core top level module that will instantiate the Fetch, Decode, Execute, Memory, Write Back, GPR, etc. modules and their interconnecting signals.
2. Design of Execute Stage with connections to various Functional Units
3. Design of ALU, Branch, Integer Multiply Functional units.
4. Forwarding logic

Session 3

Video

9/5/2019 - Video of the third session on designing the RisKy1 CPU

Code

9/5/2019 - Zip file of the System Verilog files used in the Session 3 video

Session 3 covered the following:

1. Design of Load/Store Functional Unit.
2. Design of CSR Functional Unit (this will not include the actual CSR registers as defined in Privileges spec)
3. Design of Write Back Stage

Session 4

Video

10/15/2019 - Video of the fourth session on designing the RisKy1 CPU

Code

9/20/2019 - Zip file of the System Verilog files used in the Session 4 video

Session 4 will cover the following:

1. Updates made to decode.sv, decode_core.sv, execute.sv, gpr.sv, ls_fu.sv and RisKy1_core.sv
2. New modules csr.sv (not csr_fu.sv), and fetch.sv. Most of the video is about fetch.sv

Session 5 Video 11/7/2019 - Video of the fifth session on designing the RisKy1 CPU
Code 11/6/2019 - Zip file of the System Verilog files used in the Session 5 video

Session 5 covers the following:

1. Addition of mem_io.sv, irq.sv
2. Fixes to fetch.sv, exe.sv, RisKy1.sv...
3. csr.sv is now combined with the older csr_fu.sv and the result is a new csr_fu.sv (inside execute.sv)
4. Addition of a lot of logic to csr_fu.sv is in the form of new include files csr_rd_mach.svh, csr_rd_super.svh, csr_rd_user.svh, csr_wr_mach.svh, csr_wr_super.svh, csr_wr_user.svh...

Session 6 Video TBD
Code

TBD

NOTE: This zip file will change until video is available

Session 6 will cover the following:

TBD

   

This is a new design in progress.

Current Status: Simulation of a small program called factorial which calculates the factorial of 4. Still adding updates and new code.

 

Free Software

Modelsim

Intel Modesim 19.1.0.240. This is equivalent to 10.6d. See here

 

part 1

ModelSimProSetup-19.1.0.240-windows.exe (part 1 of 2)

part 2

modelsim-part2-19.1.0.240-windows.qdz (part 2 of 2)
RISC-V Software Ecosystem See https://riscv.org/software-status/
     

 

RISC-V Specifications

See https://riscv.org/specifications to see if there are more recent versions

The RISC-V Instruction Set Manual Volume I: Unprivileged ISA
The RISC-V Instruction Set Manual Volume II: Privileged Architecture
RISC-V External Debug Support specification