RisKy1 Project File Organization
Here you will find information about how the RisKy1 project is organized.
Updated 9/29/2019
| Folders (green) and Files(orange,red) | Contents | ||||
|---|---|---|---|---|---|
| RisKy1 | |||||
| sim | ModelSim project folder | ||||
| risky1-core | First testbench used for simulating instructions running on the CPU | ||||
| instr_tests | folder to hold various software programs that could be used for testing the cpu operation | ||||
| factorial.c | C program with embedded assembly to compute the factorial of 4 | ||||
| factorial.txt | Disassembly of factorial.c | ||||
| factorial.rom | table of 32 bit ASCII hex values (instructions) for factorial.c that can be run in simulation | ||||
| rand.rom | Constrained random instructions generated by Modelsim script gen_rand_instr.do | ||||
| work | Automatcially created by Modelsim. Ok to delete contents, but not the folder. Deleting contents reduces the size of the backup file you create for this project | ||||
| gen_rand_instr.do | |||||
| gen_rand_instr.sv | |||||
| mem_arb_model.sv | Contains a simple behavioral model to arbitrate between the L1 Instruction Cacahe and L1 Data Cache with System Memory | ||||
| RisKy1.cr.mti | Created by Modelsim - do not disturb | ||||
| RisKy1.mpf | Created by Modelsim - do not disturb. This .mpf is the Modelsim Project File. Modelsim does relative accesses to other files based upon this folder location | ||||
| sdiv_tb.do | Signed/unsigned 32x32 integer divider producing integer result and remainder | ||||
| sdiv_tb.sv | Testbench for signed/unsinged integer divider sdiv_N_by_N.sv | ||||
| top_tb1.do | This is the script used in the modelsim Transcript window to compile the files, create a waveform viewwing window and run the simulation | ||||
| top_tb1.sv | Top Level testbench to run the CPU with caches and memory arbitration | ||||
| vsim.wlf | Created by Modelsim - can be deleted when you delete the contents of the work folder to reduce backup size | ||||
| wave_sdiv.do | created with various signals from inside the CPU design. Dislayed during simulation - see sdiv_tb.do | ||||
| wave_tb1.do | created with various signals from inside the CPU design. Dislayed during simulation - see top_tb1.do | ||||
| Folders & Files | FileContents | ||||
| src | Verilog & System Verilog source files | ||||
| cpu_src | files related to the CPU core | ||||
| alu_fu.sv | ALU Functional Unit instantiated in execute.sv Calculates the right hand side of equations like Rd = Rs1 + Rs2, Rd = imm, Rd = Rs1 + imm | ||||
| br_fu.sv | Branch Functional Unit instantiated in execute.sv Calculates the next PC and a branch PC | ||||
| csr_fu.sv | CSR Functional Unit instantiated in execute.sv - logic & CSR registers | ||||
| csr_lo_cnt.sv | usd in csr.sv. Specifically used for the Machine Cycle Counter (CSR 12'hB00) | ||||
| csr_std_wr.sv | usd in csr.sv.Used toi create some of the CSR registers: |
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| decode.sv | DECODE stage of pipeline | ||||
| decode_core.sv | creates signals for each instruction for use in different pipeline stages | ||||
| execute.sv | EXECUTION Stage of the pipline. This module instantiate various Functional Units, CSR.sv, and logic | ||||
| fetch.sv | FETCH stage of the pipeline. Fetches instructions from external memory (such as an Instruction cache), buffers it and feeds it to the DECODE stage of the pipeline if the DECODE stage is ready for another instruction. It also looks at each instruction it pulls in to see if it's a branch type instruction so that with prediction logic it can determine the next instruction address. | ||||
| gpr.sv | Contains 32, 32-bit General Purpose Registers - i.e. the Architectural Registers | ||||
| idr_fu.sv | Integer Divide/Remainder Functional Unit | ||||
| im_fu.sv | Integer Multiply Functional Unit | ||||
| irq.sv | Interrupt Controller. Also contains mtime counter and mtimecmp registers | ||||
| L1_dcache.sv | L1 Data Cache - this is used external to the CPU if needed. For small FPGA applications, Block RAMs might be used. This is a single port cache is for single CPU use (i.e. no cache coherency) | ||||
| L1_icache.sv | L1 Instruction Cache - this is used external to the CPU if needed. For small FPGA applications, Block RAMs might be used. This is a single port cache is for single CPU use (i.e. no cache coherency) | ||||
| ls_fu.sv | Load/Store Functional Unit. Calculates the Load or Store address | ||||
| mem.sv | MEMORY stage of the pipeline. Loads/Stores to system memory if needed by an instruction. | ||||
| mem_io.sv | Determines which memory accesses go to the L1 Data Cache and which go to other memory and I/O | ||||
| pipe.sv | A set of registers (flip flops) used between pipline stage | ||||
| RisKy1_core.sv | Top level of the RisKy1 CPU core. L1 Instruction and Data caches are not part of the core, but can be used with the core if needed. | ||||
| sdiv_N_by_N.sv | N x N (currently set for 32x32) Signed/unsigned Integer Division/Remainder using a new method of division | ||||
| vedic_mult16x16.v | 16 x 16 integer multiplier used by im_fu.sv | ||||
| vedic_mult32x32 | 32 x 32 integer multiplier used by im_fu.sv | ||||
| wb.sv | Write Back stage of pipeline. Stores any needed results to the GPRs (Architectural Registers) | ||||
| debug | files used in Modesim simulations for debugging purposes - this module is NOT synthesizable | ||||
| dis_asm_RV.sv | This module will disassemble a 32/16 bit data into assembly language as strings that can be displayed during simulation | ||||
| includes | Include files used by various cpu source files | ||||
| alu_encodings.svh | information used in decode_core.sv to create signals used by various modules | ||||
| cpu_params.svh | contains parameters that can be changed by the user to affect the CPU that is built - such as Power-up Reset Vector or address location of the Core Interrupt Controller rregisters. | ||||
| cpu_structs.svh | Contains most all System Verilog packed structures used throughout the design | ||||
| csr_rd_cntr_tmr.svh | contains read logic for CSR related counter/timers | ||||
| csr_rd_mach.svh | Due to the size of the CSR logic, it was broken into sections for Machine, Supervisor and User. This is the read logic for Machine mode CSRs | ||||
| csr_rd_super.svh | ...This is the read logic for the Supervisor mode CSRs | ||||
| csr_rd_user.svh | ...This is the read logic for the User modeCSRs | ||||
| csr_regs.svh | ...This contains instantiations of all CSR registers that can be used in this design (i.e. csr_mstatus, etc..) | ||||
| csr_wr_mach.svh | ...This is the write logic and registers for Machine mode CSRs | ||||
| csr_wr_super.svh | ...This is the write logic and registers for Supervisor mode CSRs | ||||
| csr_wr_user.svh | ...This is the write logic and registers for User mode CSRs | ||||
| functions.svh | contains the bit_size function. Feed it a value (i.e. 255) and it will return a value specifying the number of bits needed to hold the value passed to it (i.e 8). If you pass 256, you'll get 9. If you pass 0 you'll get 1 | ||||
| instr_bits.svh | Bit patterns for both 32 & 16 bit instruciotns used in decoding. See decode_core.sv. Example: `define LUI 32'b???????_?????_?????_???_?????_0110111 |
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| logic_params.svh | Simple localparams for TRUE, FALSE, ONE, ZERO | ||||
| sva | System Verilog Assertion files - these are not fully fuctional yet as of 12/16/2019 | ||||
| csr_asserts.sv | Assertions to be bound to csr_fu.sv | ||||
| gpr_asserts.sv | Assertions to be bound to gpr.sv | ||||
| mem_asserts.sv | Assertions to be bound to mem.sv | ||||
| pipe_asserts.sv | Assertions to be bound to pipe.sv | ||||
| RisKy1_asserts.sv | Assertions to be bound to RisKy1_core.sv | ||||
| wb_asserts.sv | Assertions to be bound to wb.sv | ||||
