A New RTL Language
Nov. 28, 2013:
This is an idea for an RTL Language preprocessor that produces Verilog code. In the years I have been designing Verilog, I find that I use a lot of the same type of code to setup state machines. This method proposes a way to reduce the amount of coding needed to produce state machine logic. Below is a sample of a state machine using the new language, and as I have time I will explain it and show the resulting Verilog code. If anyone is interested in this, maybe it could be a collaborative project. Right now it's in its infancy. If this is of interest, please email and let me know.
First of all, notice the keywords that are used in the state machine:
1. state_name: This allows the user to give a specific name to the flip flops that make up the state machine. If this keyword is not used, an internally generated name will be created.
2. reset_state: This allows the user to specify which state is the one used on reset. If none is specifiied then the first state defined will be the one used. In the above example, that would be state IDLE
3. reset_name: This must be used to define the signal name that is used for resetting the state machine.
4. reset_type: This must be either "sync" or "async"
5. clock_name: This must be used to define the signal name that is used for clocking the state machine flip flops.
6. clock_type: posedge or negedge can be used
Also notice that both combinatorial and sequential (flip flop) are mixed within the state machine. In normal Verilog this is not allowed. One method used is to make two state machines with ALWAYS blocks that basically have the same states - one for combinatorial and one for sequential. The parser for this code will separate and produce the desired Verilog code from this single state machine. Creating state machines by this method makes it both easier to see the design better and make it faster to code in my opinion.