Project Updates

Project Updates

 

Here you will find the latest information on updates to the KPU55 CPU and C Compiler files.

 

 

 

 

Note: For any images shown below, right click on the picture and save to your desktop. Then open it. Some pics may be larger than 2K pixels in width.

Feb 16, 2016: Added "How to ..." Install XIlinx ISE 14.7 and Compile Xilinx Libraries for ModelSim.
File Organization webpage changes/updates

Sneek peek at a new Branch Taken simulation using the new Method 3 of Branch Misprediction Elimination. This snippet of simulation is in the Execute stage, Look at the asm instruction. I realize this doesn't really show much or prove anything, but this is how all Branch Takens perform now. The appropriate instruction for a Branch Taken address (PUSH R7 in this example) or Branch Not Taken will always be in the next clock cycledepending on the branch condition. The sel_out = 1 specifies the branch will be taken. The delay between the PUSH R7 and the MOV R7, SP has to do with there's no forwarding logic for the SP (stack pointer) yet.

Notice this Branch Taken is relative to the Program Counter and has a negative offset (backward going type)

Here's another Branch Taken with a positive displacement that is forward going.


Dec 3. 2015: Addition of more debug code that allows CPU opcode disassembly in testbench runtime simulation. See highlighted line in simulation.

Dec 2, 2015: Begain debugging KPU55 code and testbench code.

Dec 1, 2015: Been working on each of the 5 pipeline stages. Created a simple Block RAM for general CPU memory use. Created Instruction ROM for the KPU55 machine code to be stored in. Created a kpu55_tb.v test simulation and kpu55_tb.do ModelSim test script to run the simulation - work in progress.

Nov 24, 2015. Created this page - Project Updates. Working on the KPU55 CPU pipeline stages Verilog code. Updates to the Theory & Operation webpage.