File Organization

KPU55 Project File Organization

 

Here you will find information about how the KPU55 projects are organized.

 

 

 


 

Folder files contents
KPU55    
  compiler_src contains all the .c, .h, parser.y and scanner.l files needed to create the C compiler
  ISE KPU55 FPGA project folder
  sim KPU55 ModelSim project folder
  src KPU55 Verilog source files
  Makefile This is the make file used to create kpu55asm.exe cross-compiler which can then be used to compile a C language file into KPU55 executable code

 

Folder files contents
compiler_src    
  cpu_defs.h User definitions related to KPU55 CPU. Can be changed for a different CPU.
  genASM.c code to allow assembly language instructions within the C code
  gencode.c Generates assembly code based on nodes created by node_functions.c
  genINSTR.c High level generic assembly language instructions that are eventually generated by user_gen_instr.c
  kcc.h Contains function prototypes, structs, C language basic instruction types used, and some external variables
  main.c Opens source file to compile and saves binary/assembly code
  makefile used to create the KCC cross compiler in Cygwin
  node_functions.c The parser.y code calls/uses this file to generate an Abstract Syntax Tree
  parser.y Compiled by Bison to generate nodes/AST
  scanner.l Compiled by Flex to generate tokens for parser.y
  show.c used to output C and assembly source together
  user_gen_instr.c Generates assembly specific to the CPU being used

 

Folder files contents
src    
  alu.v Verlog KPU55 Arithmetic Logic Unit
  bti.v ..part of new pipeline/logic to eliminate branch mispredictions
  cpu_params.h Definitions specific to KPU55 CPU
  debug_asm.h Definitions that can be used to debug assembly language in ModelSim simulations. This makes debugging code in simulation much easier. Instead of seeing binary/hex values for instructions, you can see ASCII text in the waveforms - i.e. "POP R4", "ADD R5, R1, R2", "INC R2", etc..
  decode.v Verilog code of 2nd pipeline stage
  execute.v Verilog code of 3rd pipeline stage
  fetch.v Verilog code of 1st pipeline stage
  functions.h contains compile time functions bit_size() and hextoascii(). Used by kpu55.v
  id_pipe.v ..part of new pipeline/logic to eliminate branch mispredictions
  kpu55.v Verilog KPU55 CPU code - can be used in an FPGA or ASIC along with memory and various I/O
  logic_params.h Definitins of TRUE, FALSE, etc..
  mem.v Verilog code of 4th pipeline stage
  ram.v Verilog Instantation and logic of RAM memory for the CPU
  wb.v Verilog code of 5th pipeline stage
     

 

 

To use these files with gcc, Flex and Bison, see the "How to..." about setting up Cygwin and how to build the project.