KPU5 Project

Welcome to the KPU5 Project web pages

This website contains information for the KPU5 CPU. It will be a RISC-V pipelined CPU using a multi- branch method.

Initial CPU will be based onthe RV32I instruction set. The goal is to keep the core simple enough to use in FPGA's







Goals include:

1. A documented Verilog design

2. Making a 32 bit pipelined CPU that's small and fast for FPGAs.

3. Tutorials for others to learn the how to install FPGA tools, create projects, compile the KPU5 for use in an FPGA, program an FPGA, creating code using the RISC-V compiler that will produce machine code for KPU5, tutorials, etc.. Basically a website of things and ideas for those who haven't designed or used CPUs.

Since I am currently working on an Out of Order CPU, this project is on hold - although I may gradually update it,

This "wiki" will explain how to setup this project on a Windows 7 or 10 machine in the "How to..." section. It uses Cygwin tools gcc, flex and bison for compiling the C code.

For questions or comments about this "wiki" or to get a copy of the latest source, please contact Kirk Weedman - get my contact info from my resume on my main website webpage

Getting Started with the KPU5 CPU

1. You will need to understand the Verilog Language. You can watch a series of 10 video lectures where I teach Verilog here

2. You will need to install the RISC-V compiler tools.

3. Learn how to use the RISC-V compiler to create assembly language in the "How to.." section

4. It is highly recommended you have a Verilog simulator such as ModelSim to be able to debug your FPGA project and be able to run Verilog simulations

5. Study the design of the KPU5 in the "Theory and Operation" section.

6. Download the source files for KPU5

7. Download the Verilog source and creating your FPGA project - such as Xilinx ISE 14.7