Theory and Operation
Here you will find links to various information discussing theory and operation of the KPU5 CPU
KPU5 - Verilog code
cpu_params.h | CPU specific parameters - opcodes, sizes of memory, registers, etc.. |
functions.h | |
logic_params.h | |
debug_asm.h | |
kpu5.v | top level of CPU |
fetch.v | 1st stage of pipeline - fetch and branch logic |
decode.v | 2nd stage of pipline |
execute.v | 3rd stage of pipeline |
alu.v | ALU logic used in execute.v |
mem.v | 4th stage of pipeline |
wb.v | 5th stage of pipeline |
ram.v | Code to instantiate Data Memory (Xilinx Block RAMs) for the CPU to use in an FPGA |