HDL Express

Welcome to HDL Express, the personal webpages of Kirk Weedman

HDL stands for Hardware Description Language.

This website also contains information on various Verilog/FPGA tutorials, Alternative Energy projects, and the progress of a new CPU architecture that I'm designing.

I'm an electronic design engineer specializing in contract Verilog RTL FPGA design, functional verification, simulation and debug. I have a varied background in other disciplines too.

My resume: Download the PDF version here. Download Word format here

Currently available for new FPGA design contract work.

 

Oct. 28, 2016: Current Status of the new Out of Order CPU Architecture.

This architecture is not like the typical OoO architectures being used today and the goal is to improve OoO IPC.

I'm looking for possible help. Read my OFFER to join in helping me progress faster on this new architecture.

See CPU History for more information about the progress on this architecture

See Branch Prediction Elimination for more info about the progress on this method.

1. Current simple block diagram of design

0 1 2 3 ---> Decode & Tag #0 ---> Microcode #0 --->
D.C.
---> LLRS #0 --->

Out of Order
Issue & Execute

(i.e. pool of ALU, BR, LD, ST ... Functional UNits)

----> ROB & Commit in order
Fetch                
          Decode & Tag #1 ---> Microcode #1 ---> ---> LLRS #1 ---> ---->
                         
          Decode & Tag #2 ---> Microcode #2 ---> ---> LLRS #2 ---> ---->
         

...

 

...

         
          Decode & Tag #N-1 ---> Microcode #N-1 ---> ---> LLRS #3 ---> ---->
                   

...

   
        N nstructions,Decode
and Tag
  N Microcode   ---> LLRS #M-1 ---> ---->
          Engines            
                    M LLRS modules   multiple instructions presented to ROB/commit
          ...   ...   ...   ...        

2. Nov. 27, 2016: First 100 instructions executed in 31 clocks. Forwarding logic appears to be working well.

3. Debugging instructions & flow through all stages

4. Debugging the armv7_disasm.v module that disassembles the instructions into an ASCII string thats displays disasembled instructions at various locations throughout the design during simulation. If you are interested in obtaining this module to use in Verilog simulations for ARMv-7, AND you are willing to help debug it, please email me.

 

More details on specific modules:

cpu_params.h - written. Currently debugging

armv7_disasm.v - 82% written. Currently debugging.

kpu_oooe.v - top level module 70% written. Currently debugging

fetch.v - 75% written (missing code for branch prediction elimination related logic). Currently debugging

decode.v - Most used instructions completed. Needs more logic for instructions not yet implemented. Currently debugging.

arm_micro.v - structure & data for ROM/RAM microcode table.Currently debugging.

dependency_control.v - 100% written. Currently debugging.

llrs.v - Linked List Reservation Stations (not similar to any known RS) 100% written. These are linked list type queues. Currently debugging.

gpr.v - 90% written. Contains CPU architectural registers and read/write logic connected to them.

commit.v - 85% written. This commits/retires instructions (multiple per clock if available) In Order.

llrs.v and Issue/Execite operate Out of Order.

Issue/Execute - this is actually a collection of the modules below with controlling logic. Multiple units of each for the "pool" to which certain instructions are routed for execution.

alu_functional_unit.v - ARMv7 ALU logic. 90% written. Contains Logical functions, add, subtract, 16x16, 16x32, and 32x32 integer multipliers. Using vedic style integer multipiers for now.

br_functional_unit.v - 15% written - enough to just pass instructions on to commit.v so they don't hold up the data processing instructions I'm currently debugging.

fm_functional_unit.v - floating point multiply functional unit. not written

fa_functional_unit.v - floating point addition functional unit. not written

ls_functional_unit.v - Load/Store functional unit. not written

top_tb1.v - Top level test bench #1. There's enough written to start the debug process.

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